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single-channel, 128-/64-/32-position, i 2 c, 8% resistor tolerance, nonvolatile digital potentiometer data sheet ad5110 / ad5112 / ad5114 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features single-channel, 128-/64-/32-position resolution 5 k, 10 k, 80 k nominal resistance maximum 8% nominal resistor tolerance error low wiper resistance 6 ma maximum wiper current density resistor tolerance stored in eeprom (0.1% accuracy) rheostat mode temperature coefficient: 35 ppm/c potentiometer mode temperature coefficient: 5 ppm/c 2.3 v to 5.5 v single-supply operation 1.8 v to 5.5 v logic supply operation power-on eeprom refresh time < 50 s i 2 c-compatible interface wiper setting and eeprom readback 50-year typical data retention at 125c 1 million write cycles wide operating temperature: ?40c to +125c thin, 2 mm 2 mm 0.55 mm 8-lead lfcsp package applications mechanical potentiometer replacement portable electronics level adjustment audio volume control low resolution dac lcd panel brightness and contrast control programmable voltage to current conversion programmable filters, delays, time constants feedback resistor programmable power supply sensor calibration functional block diagram power-on reset v logic v dd data data sda a w b scl eeprom ad5110/ad5112/ad5114 rdac register gnd i 2 c serial interface 09582-001 figure 1. general description the ad5110 / ad5112/ ad5114 provide a nonvolatile solution for 128-/64-/32-position adjustment applications, offering guaranteed low resistor tolerance errors of 8% and up to 6 ma current density in the a, b, and w pins. the low resistor tolerance, low nominal temperature coefficient and high bandwidth simplify open-loop applications, as well as tolerance matching applications. the new low wiper resistance feature minimizes the wiper resistance in the extremes of the resistor array to only 45 , typical. the wiper settings are controllable through an i 2 c-compatible digital interface that is also used to readback the wiper register and eeprom content. resistor tolerance is stored within eeprom, providing an end-to-end tolerance accuracy of 0.1%. the ad5110 / ad5112/ ad5114 are available in a 2 mm 2 mm lfcsp package. the parts are guaranteed to operate over the extended industrial temperature range of ?40c to +125c. table 1. 8% resistance tolerance family model resistance (k) position interface ad5110 10, 80 128 i 2 c ad5111 10, 80 128 up/down ad5112 5, 10, 80 64 i 2 c ad5113 5, 10, 80 64 up/down ad5116 5, 10, 80 64 push-button ad5114 10, 80 32 i 2 c ad5115 10, 80 32 up/down
ad5110/ad5112/ad5114 data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ad5110 .......................................... 3 electrical characteristics ad5112 .......................................... 5 electrical characteristics ad5114 .......................................... 7 interface timing specifications .................................................. 9 shift register and timing diagram ......................................... 10 absolute maximum ratings .......................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configuration and function descriptions ........................... 12 typical per formance characteristics ........................................... 13 test circuits ..................................................................................... 18 theory of operation ...................................................................... 19 rdac register and eeprom .................................................. 19 i 2 c serial data interface ............................................................ 19 input shift register .................................................................... 20 write operation .......................................................................... 21 eeprom write acknowlegde polling .................................... 23 read operation ........................................................................... 23 reset ............................................................................................. 23 shutdown mode ......................................................................... 23 rdac architecture .................................................................... 24 programming the variabl e resistor ......................................... 24 programming the potentiometer divider ............................... 25 terminal voltage operating range ......................................... 26 power - up sequence ................................................................... 26 layout and power supply biasing ............................................ 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 10 /11 revision 0: initial version
data sheet ad5110/ad5112/ad5114 rev. 0 | page 3 of 28 specifications electrical characteristics ad5110 10 k and 80 k versions: v dd = 2.3 v to 5.5 v, v logic = 1.8 v to v dd , v a = v dd , v b = 0 v, ?40c < t a < +125c, unless otherwise noted. table 2. parameter symbol test conditions/comments min typ 1 max unit dc characteristicsrheostat mode resolution n 7 bits resistor integral nonlinearity 2 r-inl r ab = 10 k, v dd = 2.3 v to 2.7 v ?2.5 0.5 +2.5 lsb r ab = 10 k, v dd = 2.7 v to 5.5 v ?1 0.25 +1 lsb r ab = 80 k ?0.5 0.1 +0.5 lsb resistor differential nonlinearity 2 r-dnl ?1 0.25 +1 lsb nominal resistor tolerance r ab /r ab ?8 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wiper resistance r w code = zero scale 70 140 r bs code = bottom scale 45 80 r ts code = top scale 70 140 dc characteristicspotentiometer divider mode integral nonlinearity 4 inl ?0.5 0.15 +0.5 lsb differential nonlinearity 4 dnl ?0.5 0.15 +0.5 lsb full-scale error v wfse r ab = 10 k ?2.5 lsb r ab = 80 k ?1.5 lsb zero-scale error v wzse r ab = 10 k 1.5 lsb r ab = 80 k 0.5 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 10 ppm/c resistor terminals maximum continuous i a , i b , and i w current 3 r ab = 10 k ?6 +6 ma r ab = 80 k ?1.5 +1.5 ma terminal voltage range 5 gnd v dd v capacitance a, capacitance b 3 c a , c b f = 1 mhz, measured to gnd, code = half scale, v w = v a = 2.5 v or v w = v b = 2.5 v 20 pf capacitance w 3 c w f = 1 mhz, measured to gnd, code = half scale, v a = v b = 2.5 v 35 pf common-mode leakage current 3 v a = v w = v b ?500 15 +500 na digital inputs input logic 3 high v inh v logic = 1.8 v to 2.3 v 0.8 v logic v v logic = 2.3 v to 5.5 v 0.7 v logic v low v inl v logic = 1.8 v to 2.3 v 0.2 v logic v v logic = 2.3 v to 5.5 v 0.3 v logic v input hysteresis 3 v hyst 0.1 v logic v input current 3 i n 1 a input capacitance 3 c in 5 pf digital output (sda) output low voltage 3 v ol i sink = 3 ma 0.2 v i sink = 6 ma 0.4 v three-state leakage current ?1 +1 a three-state output capacitance 3 2 pf
ad5110/ad5112/ad5114 data sheet rev. 0 | page 4 of 28 parameter symbol test conditions/comments min typ 1 max unit power supplies single-supply power range 2.3 5.5 v logic supply range 1.8 v dd v positive supply current i dd v dd = 5 v 750 na eemem store current 3 , 6 i dd_nvm_store 2 ma eemem read current 3 , 7 i dd_nvm_read 320 a logic supply current i logic v ih = v logic or v il = gnd 30 na power dissipation 8 p diss v ih = v logic or v il = gnd 5 w power supply rejection 3 psr ?v dd /?v ss = 5 v 10% r ab = 10 k ?50 db r ab = 80 k ?64 db dynamic characteristics 3 , 9 bandwidth bw code = half scale, ?3 db r ab = 10 k 2 mhz r ab = 80 k 200 khz total harmonic distortion thd v a = v dd /2 +1 v rms, v b = v dd /2, f = 1 khz, code = half scale r ab = 10 k ?80 db r ab = 80 k ?85 db v w settling time t s v a = 5 v, v b = 0 v, 0.5 lsb error band r ab = 10 k 3 s r ab = 80 k 12 s resistor noise density e n_wb code = half scale, t a = 25c, f = 100 khz r ab = 10 k 9 nv/hz r ab = 80 k 20 nv/hz flash/ee memory reliability 3 endurance 10 t a = 25c 1 mcycles 100 kcycles data retention 11 50 years 1 typical values represent av erage readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v. 2 resistor position nonlinearity error (r-inl) is the deviatio n from an ideal value measured be tween the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. the maximum wiper current is li mited to 0.75 v dd /r ab . 3 guaranteed by design and characterization, not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operat ing conditions. 5 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 6 different from operating current; supply curr ent for nvm program lasts approximately 30 ms. 7 different from operating current; supply curr ent for nvm read lasts approximately 20 s. 8 p diss is calculated from (i dd v dd ) + (i logic v logic ). 9 all dynamic characteristics use v dd = 5.5 v, and v logic = 5 v. 10 endurance is qualified at 100,000 cycles per jedec standard 22, me thod a117 and measured at 150c. 11 retention lifetime equivalent at junction temperature (t j ) = 125c per jedec standard 22, metho d a117. retention lifet ime based on an activa tion energy of 1 ev derates with junction temperature in the flash/ee memory.
data sheet ad5110/ad5112/ad5114 rev. 0 | page 5 of 28 electrical characteristics ad5112 5 k, 10 k, and 80 k versions: v dd = 2.3 v to 5.5 v, v logic = 1.8 v to v dd , v a = v dd , v b = 0 v, ?40c < t a < +125c, unless otherwise noted. table 3. parameter symbol test conditions/comments min typ 1 max unit dc characteristicsrheostat mode resolution n 6 bits resistor integral nonlinearity 2 r-inl r ab = 5 k, v dd = 2.3 v to 2.7 v ?2.5 0.5 +2.5 lsb r ab = 5 k, v dd = 2.7 v to 5.5 v ?1 0.25 +1 lsb r ab = 10 k ?1 0.25 +1 lsb r ab = 80 k ?0.25 0.1 +0.25 lsb resistor differential nonlinearity 2 r-dnl +1 0.25 +1 lsb nominal resistor tolerance r ab /r ab ?8 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wiper resistance r w code = zero scale 70 140 r bs code = bottom scale 45 80 r ts code = top scale 70 140 dc characteristicspotentiometer divider mode integral nonlinearity 4 inl ?0.5 0.15 +0.5 lsb differential nonlinearity 4 dnl ?0.5 0.15 +0.5 lsb full-scale error v wfse r ab = 5 k ?2.5 lsb r ab =10 k ?1.5 lsb r ab = 80 k ?1 lsb zero-scale error v wzse r ab = 5 k 1.5 lsb r ab =10 k 1 lsb r ab = 80 k 0.25 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 10 ppm/c resistor terminals maximum continuous i a , i b , and i w current 3 r ab = 5 k, 10 k ?6 +6 ma r ab = 80 k ?1.5 +1.5 ma terminal voltage range 5 gnd v dd v capacitance a, capacitance b 3 c a , c b f = 1 mhz, measured to gnd, code = half scale, v w = v a = 2.5 v or v w = v b = 2.5 v 20 pf capacitance w 3 c w f = 1 mhz, measured to gnd, code = half scale, v a = v b = 2.5 v 35 pf common-mode leakage current 3 v a = v w = v b ?500 15 +500 na digital inputs input logic 3 high v inh v logic = 1.8 v to 2.3 v 0.8 v logic v v logic = 2.3 v to 5.5 v 0.7 v logic v low v inl v logic = 1.8 v to 2.3 v 0.2 v logic v v logic = 2.3 v to 5.5 v 0.3 v logic v input hysteresis 3 v hyst 0.1 v logic v input current 3 i n 1 a input capacitance 3 c in 5 pf digital output (sda) output low voltage 3 v ol i sink = 3 ma 0.2 v i sink = 6 ma 0.4 v three-state leakage current ?1 +1 a three-state output capacitance 3 2 pf
ad5110/ad5112/ad5114 data sheet rev. 0 | page 6 of 28 parameter symbol test conditions/comments min typ 1 max unit power supplies single-supply power range 2.3 5.5 v logic supply range 1.8 v dd v positive supply current i dd v dd = 5 v 750 na eemem store current 3 , 6 i dd_nvm_store 2 ma eemem read current 3 , 7 i dd_nvm_read 320 a logic supply current i logic v ih = v logic or v il = gnd 30 na power dissipation 8 p diss v ih = v logic or v il = gnd 5 w power supply rejection 3 psr ?v dd /?v ss = 5 v 10% r ab = 5 k ?43 db r ab =10 k ?50 db r ab = 80 k ?64 db dynamic characteristics 3 , 9 bandwidth bw code = half scale ? 3 db r ab = 5 k 4 mhz r ab = 10 k 2 mhz r ab = 80 k 200 khz total harmonic distortion thd v a = v dd /2 + 1 v rms, v b = v dd /2, f = 1 khz, code = half scale r ab = 5 k ?75 db r ab = 10 k ?80 db r ab = 80 k ?85 db v w settling time t s v a = 5 v, v b = 0 v, 0.5 lsb error band s r ab = 5 k 2.5 s r ab = 10 k 3 s r ab = 80 k 10 s resistor noise density e n_wb code = half scale, t a = 25c, f = 100 khz r ab = 5 k 7 nv/hz r ab = 10 k 9 nv/hz r ab = 80 k 20 nv/hz flash/ee memory reliability 3 endurance 10 t a = 25c 1 mcycles 100 kcycles data retention 11 50 years 1 typical values represent av erage readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v. 2 resistor position nonlinearity error (r-inl) is the deviatio n from an ideal value measured be tween the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. the maximum wiper current is li mited to 0.75 v dd /r ab . 3 guaranteed by design and characterization, not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operat ing conditions. 5 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 6 different from operating current; supply curr ent for nvm program lasts approximately 30 ms. 7 different from operating current; supply curr ent for nvm read lasts approximately 20 s. 8 p diss is calculated from (i dd v dd ) + (i logic v logic ). 9 all dynamic characteristics use v dd = 5.5 v, and v logic = 5 v. 10 endurance is qualified at 100,000 cycles per jedec standard 22, me thod a117 and measured at 150c. 11 retention lifetime equivalent at junction temperature (t j ) = 125c per jedec standard 22, metho d a117. retention lifet ime based on an activa tion energy of 1 ev derates with junction temperature in the flash/ee memory.
data sheet ad5110/ad5112/ad5114 rev. 0 | page 7 of 28 electrical characteristics ad5114 10 k and 80 k versions: v dd = 2.3 v to 5.5 v, v logic = 1.8 v to v dd , v a = v dd , v b = 0 v, ?40c < t a < +125c, unless otherwise noted. table 4. parameter symbol test conditions/comments min typ 1 max unit dc characteristicsrheostat mode resolution n 5 bits resistor integral nonlinearity 2 r-inl ?0.5 +0.5 lsb resistor differential nonlinearity 2 r-dnl ?0.25 +0.25 lsb nominal resistor tolerance r ab /r ab ?8 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wiper resistance r w code = zero scale 70 140 r bs code = bottom scale 45 80 r ts code = top scale 70 140 dc characteristicspotentiometer divider mode integral nonlinearity 4 inl ?0.25 +0.25 lsb differential nonlinearity 4 dnl ?0.25 +0.25 lsb full-scale error v wfse r ab = 10 k ?1 lsb r ab = 80 k ?0.5 lsb zero-scale error v wzse r ab = 10 k 1 lsb r ab = 80 k 0.25 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 10 ppm/c resistor terminals maximum continuous i a , i b , and i w current 3 r ab = 10 k ?6 +6 ma r ab = 80 k ?1.5 +1.5 ma terminal voltage range 5 gnd v dd v capacitance a, capacitance b 3 c a , c b f = 1 mhz, measured to gnd, code = half scale, v w = v a = 2.5 v or v w = v b = 2.5 v 20 pf capacitance w 3 c w f = 1 mhz, measured to gnd, code = half scale, v a = v b = 2.5 v 35 pf common-mode leakage current 3 v a = v w = v b ?500 15 +500 na digital inputs input logic 3 high v inh v logic = 1.8 v to 2.3 v 0.8 v logic v v logic = 2.3 v to 5.5 v 0.7 v logic v low v inl v logic = 1.8 v to 2.3 v 0.2 v logic v v logic = 2.3 v to 5.5 v 0.3 v logic v input hysteresis 3 v hyst 0.1 v logic v input current 3 i n 1 a input capacitance 3 c in 5 pf digital output (sda) output low voltage 3 v ol i sink = 3 ma 0.2 v i sink = 6 ma 0.4 v three-state leakage current ?1 +1 a three-state output capacitance 3 2 pf
ad5110/ad5112/ad5114 data sheet rev. 0 | page 8 of 28 parameter symbol test conditions/comments min typ 1 max unit power supplies single-supply power range 2.3 5.5 v logic supply range 1.8 v dd v positive supply current i dd v dd = 5 v 750 na eemem store current 3 , 6 i dd_nvm_store 2 ma eemem read current 3 ,7 i dd_nvm_read 320 a logic supply current i logic v ih = v logic or v il = gnd 30 na power dissipation 8 p diss v ih = v logic or v il = gnd 5 w power supply rejection 3 psr ?v dd /?v ss = 5 v 10% r ab = 10 k ?50 db r ab = 80 k ?64 db dynamic characteristics 3 , 9 bandwidth bw code = half scale, ?3 db r ab = 10 k 2 mhz r ab = 80 k 200 khz total harmonic distortion thd v a = v dd /2 + 1 v rms, v b = v dd /2, f = 1 khz, code = half scale r ab = 10 k ?80 db r ab = 80 k ?85 db v w settling time t s v a = 5 v, v b = 0 v, 0.5 lsb error band r ab = 10 k 2.7 s r ab = 80 k 9.5 s resistor noise density e n_wb code = half scale, t a = 25c, f = 100 khz r ab = 10 k 9 nv/hz r ab = 80 k 20 nv/hz flash/ee memory reliability 3 endurance 10 t a = 25c 1 mcycles 100 kcycles data retention 11 50 years 1 typical values represent av erage readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v. 2 resistor position nonlinearity error (r-inl) is the deviatio n from an ideal value measured be tween the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. the maximum wiper current is li mited to 0.75 v dd /r ab . 3 guaranteed by design and characterization, not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operat ing conditions. 5 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 6 different from operating current; supply curr ent for nvm program lasts approximately 30 ms. 7 different from operating current; supply curr ent for nvm read lasts approximately 20 s. 8 p diss is calculated from (i dd v dd ) + (i logic v logic ). 9 all dynamic characteristics use v dd = 5.5 v, and v logic = 5 v. 10 endurance is qualified at 100,000 cycles per jedec standard 22, me thod a117 and measured at 150c. 11 retention lifetime equivalent at junction temperature (t j ) = 125c per jedec standard 22, metho d a117. retention lifet ime based on an activa tion energy of 1 ev derates with junction temperature in the flash/ee memory.
data sheet ad5110/ad5112/ad5114 rev. 0 | page 9 of 28 interface timing spe cifications v logic = 1.8 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 5. parameter 1 test conditions / comments min typ max unit description f scl 2 standard mode 100 khz serial clock frequency fast mode 400 khz t 1 standard mode 4.0 s t high , scl high time fast mode 0.6 s t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s t 3 standard mode 250 ns t su;dat , data setup t ime fast mode 100 ns t 4 standard mode 0 3.45 s t hd; dat , data hold time fast mode 0 0.9 s t 5 standard mode 4.7 s t su;sta , setup time for a repeated start condition fast mode 0.6 s t 6 standard mode 4 s t hd;sta , hold time (repeated) start condition fast mode 0.6 s t 7 standard mode 4.7 s t buf , bus free time between a stop and a start condition fast mode 1.3 s t 8 standard mode 4 s t su;sto , setup time for stop condition fast mo de 0.6 s t 9 standard mode 1000 ns t rda , rise time of sda signal fast mode 20 + 0.1 c l 300 ns t 10 standard mode 300 ns t fda , fall time of sda signal fast mode 20 + 0.1 c l 300 ns t 11 standard mode 1000 ns t rcl , rise time of scl signal fast mode 20 + 0.1 c l 300 ns t 11a standard mode 1000 ns t rcl1 , rise time of scl signal after a repeated start condition and after an acknowledge bit. fast mode 20 + 0.1 c l 300 ns t 12 standard mode 300 ns t fcl , fall time of scl signal fast mode 20 + 0.1 c l 300 ns t sp 3 fast mode 0 50 ns pulse width of suppressed spike t eeprom_program 4 15 50 ms memory program time t power_up 5 50 s power - on eeprom restore time t reset 25 s reset eeprom restore tim e 1 maximum bus capacitance is limited to 400 pf. 2 the sda and scl timing is measured with the input filters enabled. switching off the input filters improves the transfer rate but has a negative effect on emc behav ior of the part. 3 input filtering on the scl and sda inputs suppress noise spikes that are less than 50 ns for fast mode. 4 eeprom program time depends on the temperature and eeprom write cycles. higher timing is expected at a lower temperature and highe r write cycles. 5 maximum time after v dd is equal to 2.3 v.
ad5110/ad5112/ad5114 data sheet rev. 0 | page 10 of 28 shift register and timing diagram data bits db7 (msb) db0 (lsb) d7 d6 d5 d4 d3 d2 d1 d0 control bits c0c1 c2 0000 0 09582-002 figure 2. input register content t 12 t 11 t 2 t 6 scl t 1 t 6 t 5 t 4 t 3 t 10 t 9 t 8 t 7 sda ps s p 09582-003 figure 3. 2-wire serial interface timing diagram
data sheet ad5110/ad5112/ad5114 rev. 0 | page 11 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to gnd C 0.3 v to +7.0 v vlogic to gnd C 0.3 v to +7.0 v v a , v w , v b to gnd gnd ? 0.3 v to v dd + 0.3 v i a , i w , i b pulsed 1 frequency > 10 khz r aw = 5 k? and 10 k? 6 ma/d 2 r aw = 80 k? 1.5 ma/d 2 frequency 10 khz r aw = 5 k? and 10 k? 6 ma/d 2 r aw = 80 k? 1.5 ma/d 2 continuous r aw = 5 k? and 10 k? 6 ma r aw = 80 k? 1.5 ma digital inputs sda and scl ? 0.3 v to +7 v or v logic + 0.3 v (whichever is less) operating temperature range 3 ? 40c to +125c m aximum junction temperature (t j max) 150c storage temperature range ? 65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec package power dissipation (t j max ? t a )/ ja 1 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w t erminals at a given resistance. 2 pulse duty factor. 3 includes programming of eeprom memory. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditi ons above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is defined by jedec specification jesd - 51, and the value is dependent on the test board and test environment. table 7 . thermal resistance package type ja jc unit 8- lead lfcsp 90 1 25 c/w 1 jedec 2s2p test board, still air (0 m/s ec air flow). esd caution
ad5110/ad5112/ad5114 data sheet rev. 0 | page 12 of 28 pin con figuration and funct ion descriptions t op view (not to scale) ad5 1 10/ ad5 1 12/ ad5 1 14 3 w 4 b 1 v dd 2 a 6 scl 5 gnd 8 v logic 7 sda 09582-004 notes 1. the exposed p ad is internal l y flo a ting. figure 4 . pin configuration table 8 . pin function descriptions pin no. mnemonic description 1 v dd positive power supply; 2.3 v to 5.5 v. this pin should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 2 a terminal a of rdac. gnd v a v dd . 3 w wiper terminal of rdac. gnd v w v dd . 4 b terminal b of rdac. gnd v b v dd . 5 gnd ground pin, logic ground reference. 6 scl serial clock line. this pin is used in conjunction with the sda line to clock data i nto or out of the 16 - bit input registers. 7 sda serial data line. this pin is used in conjunction with the scl line to clock data into or out of the 16 - bit input registers. it is a bidirectional, open - drain data line that should be pulled to the supply wi th an external pull - up resistor. 8 v logic logic power supply; 1.8 v to v dd . this pin should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. epad exposed pad. the exposed pad is i nternally floating.
data sheet ad5110/ad5112/ad5114 rev. 0 | page 13 of 28 typical performance characteristic s ?0.06 ?0.04 code (decimal) r-in l (lsb) ?0.02 0 0.02 0.04 0.06 0.08 0.10 0 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 1 12 1 19 127 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c 09582-005 figure 5. r - inl vs. code ( ad5110 ) ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) r-in l (lsb) 09582-006 figure 6. r - inl vs. code ( ad5112 ) ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) r-in l (lsb) 09582-007 figure 7. r - inl vs. code ( ad5114 ) ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 1 12 1 19 127 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) r-dn l (lsb) 09582-008 figure 8. r - dnl vs. code ( ad5110 ) 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 09582-009 code (decimal) r-dn l (lsb) figure 9. r - dnl vs. code ( ad5112 ) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 ?0.018 ?0.016 ?0.014 ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) r-dn l (lsb) 09582-010 figure 10 . r - dnl vs. code ( ad5114 )
ad5110/ad5112/ad5114 data sheet rev. 0 | page 14 of 28 code (decimal) in l (lsb) 0 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 1 12 1 19 127 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c 09582-0 1 1 figure 11 . inl vs. code ( ad5110 ) 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 code (decimal) in l (lsb) 09582-012 figure 12 . inl vs. code ( ad5112 ) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 code (decimal) in l (lsb) 09582-013 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c figure 13 . inl vs. code ( ad5114 ) ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 1 12 1 19 127 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c 09582-014 code (decimal) dn l (lsb) figure 14 . dnl vs. code ( ad5110 ) ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) 09582-015 dn l (lsb) figure 15 . dnl vs. code ( ad5112 ) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 code (decimal) dn l (lsb) 09582-016 ?0.016 ?0.014 ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c figure 16 . dnl vs. code ( ad5114 )
data sheet ad5110/ad5112/ad5114 rev. 0 | page 15 of 28 0 100 ?100 200 300 400 supp l y current (na) 500 600 700 800 ?40 ?25 ?10 5 20 35 temper a ture (c) 50 65 80 95 1 10 125 2.3v a verage of i dd 2.3v a verage of i logic 3.3v a verage of i dd 3.3v a verage of i logic 5.0v a verage of i dd 5.0v a verage of i logic 09582-017 figure 17 . supply current vs. temperature 0 20 40 60 80 100 120 140 160 180 200 potentiometer mode tempco (ppm/c) 10k? 80k? 5k? 09582-018 0 20 40 60 code (decimal) 80 100 120 0 10 20 30 40 50 60 0 5 10 15 20 25 30 ad5 1 10 ad5 1 12 ad5 1 14 v dd = 5v figure 18 . potentiometer mode tempco ( ( v w /v w )/ t 10 6 ) vs. code 0 ? 60 ? 50 ?4 0 ?3 0 ?2 0 ?1 0 1 00m 10 m 1 m 10 0k 1 0k gain (db) frequenc y (hz) 0x20 0x10 0x08 0x04 0x02 0x01 0x00 09582-019 figure 19 . 5 k? gain vs. frequency vs. code ?0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 5.0 4.5 4.0 3.5 3.0 2.5 digi t al input vo lt age (v) supp l y curren t , i logic (ma) 2.0 1.5 1.0 0.5 0 v logic = 5.0v v logic = 3.3v v logic = 2.3v v logic = 1.8v 09582-020 figure 20 . supply current (i logic ) vs. digital input voltage 0 20 40 60 80 100 120 140 160 180 200 potentiometer mode tempco (ppm/c) 09582-021 0 20 40 60 code (decimal) 80 100 120 0 10 20 30 40 50 60 0 5 10 15 20 25 30 10k? 80k? 5k? v dd = 5v ad5 1 10 ad5 1 12 ad5 1 14 figure 21 . rheostat mode tempco ( ( r wb /r wb )/ t 10 6 ) vs. code ?5 0 ?4 0 ?3 0 ?1 0 0 1m 10m 100k 10k gain (db) frequenc y (hz) 0x40 0x10 0x04 0x02 ?2 0 ? 70 ?6 0 0x08 0x01 0x20 0x00 (0x20) (0x08) (0x02) (0x01) (0x04) (0x00) (0x10) [0x10] [0x04] [0x01] [0x00] [0x02] [0x08] ad5 1 10 (ad5 1 12) [ad5 1 14] 09582-022 figure 22 . 10 k? gain vs. frequency vs. code
ad5110/ad5112/ad5114 data sheet rev. 0 | page 16 of 28 ?6 0 ?5 0 ?4 0 ?3 0 ?1 0 0 1 0k 1 m 100 k gain (db) f r e q u e nc y ( h z) ?2 0 ? 80 ?7 0 0x40 0x10 0x04 0x02 0x08 0x01 0x20 0x00 (0x20) (0x08) (0x02) (0x01) (0x04) (0x00) (0x10) [0x10] [0x04] [0x01] [0x00] [0x02] [0x08] ad5 1 10 (ad5 1 12) [ad5 1 14] 09582-023 figure 23 . 80 k? gain vs. frequency vs. code ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10k 100k 1m 10m phase (degrees) frequenc y (hz) ful l scale half scale quarter scale ad5 1 10 r ab = 10k? 09582-024 figure 24 . normalized phase flatness vs. frequen cy 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 thd + n (db) frequenc y (hz) 20 200 2k 20k 200k 10k 5k 80k 09582-025 v dd = 5 v , v a = 2.5v + 1v rms v b = 2.5v code = half scale noise fi l ter = 22khz figure 25 . total harmonic distortion + noise (thd + n) vs. frequency 0 10 20 30 40 50 60 70 bandwidth (mhz) 80 code (decimal) 5k + 250pf 10k + 75pf 10k + 150pf 10k + 250pf 80k + 0pf 80k + 75pf 80k + 150pf 80k + 250pf 5k + 0pf 5k + 75pf 5k + 150pf 10k + 0pf 0 10 20 30 40 50 60 0 5 10 15 20 25 30 0 5 10 15 09582-026 ad5 1 10 ad5 1 12 ad5 1 14 figure 26 . maximum bandwidth vs. code vs. net capacitance 0 30 60 90 incremen t al wiper on resis t ance (?) 120 150 0 1 2 3 v dd (v) 4 5 6 5.5v 5v 3.3v 2.7v 2.3v temper a ture = 25c 09582-027 figure 27 . incremental wiper on resist ance vs. v dd thd + n (db) amplitude (v rms) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.001 0.01 0.1 1 09582-028 10k 5k 80k v dd = 5 v , v a = 2.5v + v in v b = 2.5v f in = 1khz code = half scale noise fi l ter = 22khz figure 28 . total harmonic distortion + noise (thd + n) vs. amplitude
data sheet ad5110/ad5112/ad5114 rev. 0 | page 17 of 28 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 ?1 1 3 5 time (s) rel a tive vo lt age (v) 7 9 09582-029 v dd = 5v v a = v dd v b = gnd 10k? 80k? 5k? figure 29 . maximum transition glitch 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.0005 0.0010 0.0015 0.0020 0.0025 ?400 ?500 ?600 ?300 ?200 ?100 0 100 200 300 400 500 600 cumul a tive probabilit y probabilit y densit y resis t or drift (ppm) 09582-051 figure 30 . resistor lifet ime drift ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequenc y (hz) psrr (db) 10 100 1k 10k 100k 1m 5k ? 10k ? 80k ? 09582-031 v dd = 5v 10% ac v a = 4v v b = gnd half scale t a = 25c figure 31 . power supply rejection ratio (psrr) vs. frequency ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 10k? 80k? 5k? 2.5 0.6 1.2 1.8 0 volt age (mv) time (s) v dd = 5v v a = v dd v b = gnd 09582-032 figure 32 . digital feedthrough ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1k 10k 1m 10m gain (db) frequenc y (hz) 5k ? 10k ? 80k ? 09582-033 figure 33 . shutdown isolation vs. frequency 0 1 2 3 4 5 6 7 theoretica l i max (ma) 10k ? 80k ? 5k ? 0 20 40 60 code (decimal) 80 100 120 0 10 20 30 40 50 60 0 5 10 15 20 25 30 ad5 1 10 ad5 1 12 ad5 1 14 09582-034 figure 34 . theore tical maximum current vs. code
ad5110/ad5112/ad5114 data sheet rev. 0 | page 18 of 28 test circuits figure 35 to figure 40 define the test conditions used in the specifications section. a w b nc i w dut v ms nc = no connect 09582-035 figure 35 . resistor position nonlinearity error (rheostat operation: r - inl, r - dnl) a w b du t v m s v+ v+ = v d d 1 l s b = v+ / 2 n 09582-036 figure 36 . potentiometer divider nonlinearity error (inl, dnl) + ? dut 0.1v = 0.1v i wb i wb w b nc = no connect r w a nc gnd t o v dd 09582-037 figure 37 . wiper resistance a w b v m s ~ v a v d d v+ v+ = v d d 10 % v m s % v d d % pss ( % / % ) = ps rr ( d b ) = 20 lo g v m s v d d 09582-038 figure 38 . power supply sensitivity (pss, psrr) offset gnd a b dut w +15v v in v out ad8652 ?15v 2.5v 09582-039 figure 39 . gain and phase vs. frequency dut i cm w b v dd gnd a v dd gnd gnd v dd gnd v dd 09582-040 figure 40 . common - mode leakage current
data sheet ad5110/ad5112/ad5114 rev. 0 | page 19 of 28 theory of operation the ad5110 / ad5112/ ad5114 digital programmable resistors are designed to operate as true variable resistors for analog signals within the terminal voltage range of gnd < v term < v dd . the resistor wiper position is determined by the rdac register contents. the rdac register acts as a scratchpad register that allows unlimited changes of resistance settings. the rdac register can be programmed with any position setting using the i 2 c interface. once a desirable wiper position is found, this value can be stored in the eeprom memory. thereafter, the wiper position is always restored to that position for subsequent power-up. the storing of eeprom data takes approximately 18 ms; during this time, the device is locked and does not acknowledge any new command, thus preventing any changes from taking place. rdac register and eeprom the rdac register directly controls the position of the digital potentiometer wiper. for example, when the rdac register is loaded with 0x3f (128-taps), the wiper is connected to full scale of the variable resistor. the rdac register is a standard logic register; there is no restriction on the number of changes allowed. it is possible to both write to and read from the rdac register using the i 2 c interface (see table 10). the contents of the rdac register can be stored to the eeprom using command 1 (table 10). thereafter, the rdac register is always set at that position for any future on-off-on power supply sequence. it is possible to read back the data saved into the eeprom with command 6 in table 10. in addition, the resi stor tolerance error is saved within the eeprom; this can be read back and used to calculate the end- to-end tolerance, providing an accuracy of 0.1%. low wiper resistance feature the ad5110 / ad5112/ ad5114 include extra steps to achieve a minimum resistance between terminal w and terminal a or terminal b. these extra steps are called bottom scale and top scale. at bottom scale, the typical wiper resistance decreases from 70 to 45 . at top scale, the resistance between terminal a and terminal w is decreased by 1 lsb, and the total resistance is reduced to 70 . the extra steps are not equal to 1 lsb and are not included in the inl, dnl, r-inl, and r-dnl specifications. i 2 c serial data interface the ad5110 / ad5112/ ad5114 have 2-wire i 2 c-compatible serial interfaces. these devices can be connected to an i 2 c bus as a slave device under the control of a master device. see figure 3 for a timing diagram of a typical write sequence. the ad5110 / ad5112/ ad5114 support standard (100 khz) and fast (400 khz) data transfer modes. support is not provided for 10-bit addressing and general call addressing. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7-bit slave address and an r/w bit. the slave device corresponding to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. 2. if the r/ w bit is set high, the master reads from the slave device. however, if the r/ w bit is set low, the master writes to the slave device. 3. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 4. when all data bits have been read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master brings the sda line low before the 10 th clock pulse, and high during the 10 th clock pulse to establish a stop condition. i 2 c address the ad5110 / ad5112/ ad5114 each have two different slave address options available. see table 9 for a list of slave addresses. table 9. device address selection model 7-bit i 2 c device address ad511x 1 bcpz y 2 0101111 ad511x 1 bcpz y 2 -1 0101100 1 model. 2 resistance.
ad5110/ad5112/ad5114 data sheet rev. 0 | page 20 of 28 input shift register for the ad5110 / ad5112 / ad5114 , the input shift register is 16 bits wide (see figure 2). the 16-bit word consists of five unused bits (should be set to zero), followed by three control bits, and eight rdac data bits. if the rdac register is read from or written to in the ad5112 , bit db0 is a dont care. the rdac register is read from or written to in the ad5114 , bit db0 and db1 are dont cares. data is loaded msb first (bit db15). the three control bits determine the function of the software command (table 10). figure 3 shows a timing diagram of a typical ad5110 / ad5112 / ad5114 write sequence. the command bits (cx) control the operation of the digital potentiometer and the internal eeprom. the data bits (dx) are the values that are loaded into the decoded register. table 10. command operation truth table command number command data 1 db10 db8 db7 db0 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 x x x x x x x x no operation 1 0 0 1 x x x x x x x x write contents of rdac register to eeprom 2 0 1 0 7 msb 6 5 4 3 2 1 2 0 2, 3 lsb write contents of serial register data to rdac 1 0 0 0 0 0 0 0 top scale 1 1 1 1 1 1 1 1 bottom scale 3 0 1 1 x x x x x x x a0 software shutdown 0: shutdown off 1: shutdown on 4 1 0 0 x x x x x x x x software reset: refresh rdac register with eeprom 5 1 0 1 x x x x x x x x read contents of rdac register 6 1 1 0 x x x x x x a1 a0 read contents of eeprom a1 a0 data 0 0 wiper position saved 0 1 resistor tolerance 1 x is dont care. 2 in the ad5114 , this bit is a dont care. 3 in the ad5112 , this bit is a dont care.
data sheet ad5110/ad5112/ad5114 rev. 0 | page 21 of 28 write operation when writing to the ad5110 / ad5112 / ad5 114 , the user must begin with a start command followed by an address byte (r/ w = 0), after which the ad5110 / ad5112 / ad5114 acknowledge that it is prepared to receive data by pulling sda low. two bytes of data are then written to the dac, the most significant byte , followed by the least significant byte . b oth of these data bytes are acknowledged by the ad5110 / ad5112 / ad5114 . a stop condition follows. the write operations for the ad5110 / ad5112 / ad5114 are shown in figure 41, figure 42 , and figure 43. a repeated write function gi ves the user flexibility to update the device a number of times after addressing the part only once, as shown in figure 44. scl sda st art b y master ack. b y ad5 1 10 ack. b y ad5 1 10 frame 1 seria l bus address byte frame 2 most significant d at a byte frame 3 least significant d at a byte scl (continued) sda (continued) ack. b y ad5 1 10 st op b y master 0 1 9 1 9 9 9 1 1 0 1 1 a1 a0 0 0 0 0 0 c2 c1 c0 d 7 d 6 d 5 d 4 d3 d2 d1 d0 r/w 09582-041 figure 41 . ad5110 interface write command scl sda st art b y master ack. b y ad5 1 12 ack. b y ad5 1 12 frame 1 seria l bus address byte frame 2 most significant d at a byte frame 3 least significant d at a byte scl (continued) sda (continued) ack. b y ad5 1 12 st op b y master 0 1 9 1 9 9 9 1 1 0 1 1 a1 a0 0 0 0 0 0 c2 c1 c0 d 6 d 5 d 4 d3 d2 d1 d0 0 r/w 09582-042 figure 42 . ad5112 interface write command
ad5110/ad5112/ad5114 data sheet rev. 0 | page 22 of 28 scl sda st art b y master ack. b y ad5 1 14 ack. b y ad5 1 14 frame 1 seria l bus address byte frame 2 most significant d at a byte frame 3 least significant d at a byte scl (continued) sda (continued) ack. b y ad5 1 14 st op b y master 0 1 9 1 9 9 9 1 1 0 1 1 a1 a0 0 0 0 0 0 c2 c1 c0 d 2 d1 d3 d5 d4 d0 0 0 r/w 09582-043 figure 43 . ad5114 interface write command scl sda 0 1 9 1 9 9 9 1 1 0 1 1 a1 a0 r/w 0 0 0 0 0 c2 c1 c0 d 7 d 6 d 5 d 4 d3 d2 d1 d0 scl (continued) sda (continued) scl (continued) sda (continued) scl (continued) sda (continued) 1 9 9 d7 d6 d5 d4 d3 d2 d1 d0 1 9 9 0 0 0 0 0 c2 c1 c0 frame 4 most significant d at a byte frame 5 least significant d at a byte st art b y master ack. b y ad5 1 10 ack. b y ad5 1 10 ack. b y ad5 1 10 ack. b y ad5 1 10 ack. b y ad5 1 10 st op b y master frame 1 seria l bus address byte frame 2 most significant d at a byte frame 3 least significant d at a byte 09582-044 figure 44 . ad5110 interface multiple write
data sheet ad5110/ad5112/ad5114 rev. 0 | page 23 of 28 eeprom write acknowl egde polling after each write operation to the eeprom, an internal write cycle begins. the i 2 c interface of the device is disabled. to determin e if the internal write cycle is complete and the i 2 c interface is enabled, interface polling can be executed. i 2 c interface polling can be conducted by sending a start condition, followed by the slave address and the write bit. if the i 2 c interface respon ds with an acknowledge, the write cycle is complete , and the interface is ready to proceed with further operations. otherwise, i 2 c interface polling can be repeated until it succeeds. read operation the ad5110 / ad5112 / ad5114 allow read back of the contents of the rdac register and eeprom memory through the i 2 c interface by using command 6 (see table 10). w hen reading data back from the ad5110 / ad5112 / ad5114 , the user must first issue a readback command to the device . t his begins wi th a start command , followed by an address byte (r/ w = 0), after which the ad5110 / ad5112 / ad5114 acknowl edges that it is prepared to receive data by pulling sda low. two bytes of data are then written to the ad5110 / ad5112 / ad5114 , the most significant byte followed by the least significant byte . b oth of these data bytes are acknowledged by the ad5110 / ad5112 / ad5114 . a stop condition follows. these bytes contain the read instruction, which enables readback of the rdac register, eeprom memory. the user can then read back the data . t his begins with a start command followed by an address byte (r/ w = 1), after which the device acknowledges that it is prepared to transmit data by pulling sda low. two bytes of data are then read from the device, which are both acknowledged by the master , as shown in figure 45 . a sto p condition follows. if the master does not acknowledge the first byte , then the second byte is not transmitted by the ad5110 / ad5112 / ad5114 . the ad5110 / ad5112 / ad5114 does not support repeat readback. reset the ad5110 / ad5112 / ad5114 can be reset by executing command 4 (see table 10 ). the reset command loads the rdac register with the contents of the eep rom and takes approximately 25 s. eeprom is pre - loaded to midscale at the factory, and initial power - up is, accordingly, at midscale. shutdown mode the ad5110 / ad5112 / ad5114 can be shut down by executing the software shutdown command, command 3 (see table 10 ). this feature places the rdac in a zero - power - consumption state where terminal a is open - circuite d and the wiper, terminal w is connected to terminal b but a finite wiper resistance of 45 is present. the part can be taken out of shutdown mode by executing command 3 (see table 10 ) and setting bit db0 to 0. scl sda st art b y master ack. b y ad5 1 10 ack. b y ad5 1 10 frame 1 seria l bus address byte frame 2 most significant d at a byte frame 3 least significant d at a byte scl (continued) sda (continued) ack. b y ad5 1 10 st op b y master st op b y master 0 1 9 1 9 9 9 1 1 0 1 1 a1 a0 0 0 0 0 0 c2 c1 c0 d 4 d3 d5 d7 d6 d2 d1 d0 r/w scl sda st art b y master ack. b y ad5 1 10 no ack. by master frame 1 seria l bus address byte frame 2 most significant d at a byte 0 1 9 9 1 1 0 1 1 a1 a0 0 0 0 0 0 c2 c1 c0 r/w 09582-045 figure 45 . ad5110 interface read command
ad5110/ad5112/ad5114 data sheet rev. 0 | page 24 of 28 rdac architecture to achieve optimum performance, analog devices, inc., has patented the rdac segmentation architecture for all the digital potentiometers. in particular, the ad5110/ ad5112/ ad5114 employ a two-stage segmentation approach as shown in figure 46. the ad5110/ ad5112 / ad5114 wiper switch is designed with the transmission gate cmos topology and with the gate voltage derived from v dd . r l r l r l r l r s w r s a b bs 6-bit/7-bit/8-bit address decoder ts 09582-046 figure 46. ad5110 / ad5112 / ad5114 simplified rdac circuit top scale/bottom scale architecture in addition, the ad5110/ ad5112 / ad5114 include a new feature to reduce the resistance between terminals. these extra steps are called bottom scale and top scale. at bottom scale, the typical wiper resistance decreases from 70 to 45 . at top scale, the resistance between terminal a and terminal w is decreased by 1 lsb, and the total resistance is reduced to 70 . the extra steps are not equal to 1 lsb and are not included in the inl, dnl, r-inl, and r-dnl specifications. programming the variable resistor rheostat operation8% resistor tolerance the ad5110 / ad5112/ ad5114 operate in rheostat mode when only two terminals are used as a variable resistor. the unused terminal can be floating or tied to the terminal w as shown in figure 47. a w b a w b a w b 09582-047 figure 47. rheostat mode configuration the nominal resistance between terminal a and terminal b, r ab , is available in 5 k, 10 k, and 80 k and has 32/64/128 tap points accessed by the wiper terminal. the 5-/6-/7-bit data in the rdac latch is decoded to select one of the 32/64/128 possible wiper settings. the gene ral equations for determining the digitally programmed output resistance between the w terminal and b terminal are ad5110: bs wb rr ? bottom scale (0xff) (1) w ab wb rr d dr ??? 128 )( from 0x00 to 0x80 (2) ad5112: bs wb rr ? bottom scale (0xff) (3) w ab wb rr d dr ??? 64 )( from 0x00 to 0x40 (4) ad5114: bs wb rr ? bottom scale (0xff) (5) w ab wb rr d dr ??? 32 )( from 0x00 to 0x20 (6) where: d is the decimal equivalent of the binary code in the 5-/6-/7-bit rdac register. r ab is the end-to-end resistance. r w is the wiper resistance . r bs is the wiper resistance at bottom scale
data sheet ad5110/ad5112/ad5114 rev. 0 | page 25 of 28 similar to th e mechanical potentiometer, the resistance of the rdac between the w terminal and the a terminal also produces a digitally controlled complementary resistance, r wa . r wa also gives a maximum of 8% absolute resistance error. r wa starts at the maximum resist ance value and decreases as the data loaded into the latch increases. the general equations for this operation are ad5110 : w ab aw r r r + = bottom scale (0x ff ) (7) w ab aw r r d d r + ? = 128 128 ) ( from 0x00 to 0x7f (8) ts aw r r = top scale (0x80) (9) ad5112 : w ab aw r r r + = bottom scale (0x ff ) (10) w ab aw r r d d r + ? = 64 64 ) ( from 0x00 to 0x3f (11) ts aw r r = top scale (0x40) (12) ad5114 : w ab aw r r r + = bottom scale (0x ff ) (13) w ab aw r r d d r + ? = 32 32 ) ( from 0x00 to 0x1f (14) ts aw r r = top scale (0x20) (15) where: d is the decimal equivalent of the binary code in th e 5 - / 6 - /7 - bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance . r ts is the wiper resistance at top scale. in the bottom - scale condition or top - scale condition, a finite total wiper resistance of 45 is present. regardless of which setting the part is operating in, take care to limit the current between terminal a to terminal b, terminal w to terminal a, and terminal w to terminal b, to the maximum continuous current of 6 ma or to the pulse curre nt specified in table 6 . otherwise, degradation or possible destruction of the internal switch contact can occur. calculating the actual end - to - end resistance the resistance tolerance is stored in the internal memory during factor y testing. the actual end - to - end resistance can, therefore, be calculated, which is valuable for calibration, tolerance matching, and precision applications. the resistance tolerance in percentage is stored in fixed - point format, using an 8 - bit sign magni tude binary. the data can be read back by executing command 6 and setting bit db0 (a0). the msb is the sign bit (0 = ? and 1 = +) and the next four bits are the integer part, the fractional part is represented by the three lsbs, as shown in table 11 . table 11 . tolerance format data byte db7 db6 db5 db4 db3 db2 db1 db0 sign 2 4 2 3 2 2 2 1 . 2 - 1 2 - 2 2 - 3 for example, if r ab = 10 k? and the data readback shows 01010010, the end - to - end resistance can be calculat ed as, if, db[7] is 0 = negative db[6:3] is 1010 = 10 db[2:0] is 010 = 2 2 ? 3 = 0.25 then, tolerance = ?10.25% and, therefore, r ab = 8.975 k? programming the pote ntiometer divider voltage output operation the digital potentiometer easily generates a volta ge divider at wiper - to - b and wiper - to - a that is proportional to the input voltage at a to b, as shown in figure 48 . unlike the polarity of v dd to gnd, which must be positive, voltage across a - to - b, w - to - a, and w - to - b can be at eit her polarity. a v i w b v o 09582-048 figure 48 . potentiometer mode configuration connecting terminal a to 5 v and t erminal b to ground produces an output voltage at the wiper w to terminal b ranging from 0 v to 5 v. the general equation defining the ou tput voltage at v w with respect to ground for any valid input voltage applied to terminal a and terminal b , is: b ab aw a ab wb w v r d r v r d r d v + = ) ( ) ( ) ( (16) where: r wb ( d ) can be obtained from equation 1 to equation 6. r aw ( d ) can be obtained from equation 7 to equation 15. operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, r aw and r wb , and not the absolute va lues. therefore, the temperature drift reduces to 5 ppm/c.
ad5110/ad5112/ad5114 data sheet rev. 0 | page 26 of 28 terminal voltage operating range the ad5110 / ad5112/ ad5114 are designed with internal esd diodes for protection. these diodes also set the voltage boundary of the terminal operating voltages. positive signals present on terminal a, terminal b, or terminal w that exceed v dd are clamped by the forward-biased diode. there is no polarity constraint between v a , v w , and v b , but they cannot be higher than v dd or lower than gnd. gnd v dd a w b 09582-049 figure 49. maximum terminal voltages set by v dd and gnd power-up sequence because there are diodes to li mit the voltage compliance at terminal a, terminal b, and terminal w (figure 49), it is important to power v dd first before applying any voltage to terminal a, terminal b, and terminal w. otherwise, the diode is forward-biased such that v dd is powered unintentionally. the ideal powe r-up sequence is gnd, v dd , v logic , digital inputs, and v a , v b , and v w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v dd and v logic . regardless of the power-up sequence and the ramp rates of the power supplies, once v logic is powered, the power-on preset activates, which restores eeprom values to the rdac registers. layout and power supply biasing it is always a good practice to use compact, minimum lead length layout design. the leads to the input should be as direct as possible with a minimum conductor length. ground paths should have low resistance and lo w inductance. it is also good practice to bypass the power supplies with quality capacitors. low equivalent series resistance (esr) 1 f to 10 f tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and to filter low frequency ripple. figure 50 illustrate s the basic supply bypassing configuration for the ad5110 / ad5112/ ad5114 . v dd v logic v dd + gnd c1 0.1f c2 10f v logic + c3 0.1f c4 10f ad5110/ ad5112/ ad5114 09582-050 figure 50. power supply bypassing
data sheet ad5110/ad5112/ad5114 rev. 0 | page 27 of 28 outline dimensions 1.70 1.60 1.50 0.425 0.350 0.275 063009-a top view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index area 2.00 bsc sq seating plane 0.60 0.55 0.50 1.10 1.00 0.90 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad pin 1 indicato r (r 0.15) for pro per c onnection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figur e 51 . 8 - lead frame chip scale package[lfcsp_ud] 2.00 mm 2.00 mm body, ultra thin, dual lead (cp -8- 10) dimensions shown in millimeters ordering guide model 1 r ab (k?) resolution temperature range package description i 2 c address package option branding ad5110bcpz10 - rl7 10 128 ? 40c to +125c 8 - lead lfcsp_ud 0101111 cp - 8 - 10 4j ad5110bcpz10 - 500r7 10 128 ? 40c to +125c 8- lead lfcsp_ud 0101111 cp -8- 10 4j ad5110bcpz10 -1- rl7 10 128 ? 40c to +125c 8- lead lfcsp_ud 0101100 cp -8- 10 4h ad5110bcpz80 - rl7 80 128 ? 40c to +125c 8- lead lfcsp_ud 0101111 cp -8- 10 4l ad5110bcpz80 - 500r7 80 128 ? 40c to +125c 8- lead lfcsp_ud 0101111 cp -8- 10 4l ad5110bcpz80 -1- rl7 80 128 ? 40c to +125c 8- lead lfcsp_ud 0101100 cp -8- 10 4k ad5112bcpz5 - rl7 5 64 ? 40c to +125c 8- lead lfcsp_ud 0101111 cp -8- 10 7p ad5112bcpz5 - 500r7 5 64 ? 40c to +125c 8- lead lfcsp_ud 0101111 cp -8- 10 7p ad5112bcpz5 -1- rl7 5 64 ? 40c to +125c 8- lead lfcsp_ud 0101100 cp-8- 10 7n ad5112bcpz10 - rl7 10 64 ? 40c to +125c 8- lead lfcsp_ud 0101111 cp -8- 10 7l ad5112bcpz10 - 500r7 10 64 ? 40c to +125c 8- lead lfcsp_ud 0101111 cp -8- 10 7l ad5112bcpz10 -1- rl7 10 64 ? 40c to +125c 8- lead lfcsp_ud 0101100 cp -8- 10 7k ad5112bcpz80 - rl7 80 64 ? 40c to +125c 8- lead lfcsp_ud 0101111 cp -8- 10 7r ad5112bcpz80 - 500r7 80 64 ? 40c to +125c 8- lead lfcsp_ud 0101111 cp -8- 10 7r ad5112bcpz80 - 1 - rl7 80 64 ? 40c to +125c 8 - lead lfcsp_ud 0101100 cp - 8 - 10 7q ad5114bcpz10 - rl7 10 32 ? 40c to +125c 8- le ad lfcsp_ud 0101111 cp -8- 10 81 ad5114bcpz10 - 500r7 10 32 ? 40c to +125c 8- lead lfcsp_ud 0101111 cp -8- 10 81 ad5114bcpz10 -1- rl7 10 32 ? 40c to +125c 8- lead lfcsp_ud 0101100 cp -8- 10 80 ad5114bcpz80 - rl7 80 32 ? 40c to +125c 8- lead lfcsp_wd 0101111 cp -8- 10 83 ad5114bcpz80 - 500r7 80 32 ? 40c to +125c 8- lead lfcsp_wd 0101111 cp -8- 10 83 ad5114bcpz80 -1- rl7 80 32 ? 40c to +125c 8- lead lfcsp_wd 0101100 cp -8- 10 82 eval - ad5110sdz evaluation board 1 z = rohs compliant part.
ad5110/ad5112/ad5114 data sheet rev. 0 | page 28 of 28 notes i 2 c refers to a communications protocol originall y developed by philips semiconductors (now nxp semiconductors). ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09582 - 0- 10/11(0)

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